LegUp: High-Level Synthesis for FPGA-Based Processor/Accelerator Systems
ثبت نشده
چکیده
It is generally accepted that a custom hardware implementation of a set of computations will provide superior speed and energy-efficiency relative to a software implementation. However, the cost and difficulty of hardware design is often prohibitive, and consequently, a software approach is used for most applications. In this paper, we introduce a new high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. LegUp accepts a standard C program as input and automatically compiles the program to a hybrid architecture containing an FPGAbased MIPS soft processor and custom hardware accelerators that communicate through a standard bus interface. In the hybrid processor/accelerator architecture, program segments that are unsuitable for hardware implementation can execute in software on the processor. LegUp can synthesize most of the C language to hardware, including fixedsized multi-dimensional arrays, structs, global variables and pointer arithmetic. Results show that the tool produces hardware solutions of comparable quality to a commercial high-level synthesis tool. We also give results demonstrating the ability of the tool to explore the hardware/software co-design space by varying the amount of a program that runs in software vs. hardware. LegUp, along with a set of benchmark C programs, is open source and freely downloadable, providing a powerful platform that can be leveraged for new research on a wide range of high-level synthesis topics.
منابع مشابه
Design and Implementation of Field Programmable Gate Array Based Baseband Processor for Passive Radio Frequency Identification Tag (TECHNICAL NOTE)
In this paper, an Ultra High Frequency (UHF) base band processor for a passive tag is presented. It proposes a Radio Frequency Identification (RFID) tag digital base band architecture which is compatible with the EPC C C2/ISO18000-6B protocol. Several design approaches such as clock gating technique, clock strobe design and clock management are used. In order to reduce the area Decimal Matrix C...
متن کاملSystem Level Verification and Performance Analysis for FPGA Accelerated Computers
System Level Verification and Performance Analysis for FPGA Accelerated Computers Zhimin Chen, Xu Guo, Ambuj Sinha, and Patrick Schaumont Department of Electrical and Computer Engineering Virginia Tech, Blacksburg, VA 24060, USA E-mail: {chenzm, xuguo, ambujs87, schaum}@vt.edu. As an accelerator, Field Programmable Gate Array (FPGA) has become a great potential to assist a general-purpose proce...
متن کاملPinHaT: Platform-independent Hardware Generation Tool
The PinHaT software allows the automatic generation of FPGA-based multiprocessor systems from parallel programs using Integer Linear Programming for high-level synthesis and the vendor's tool-chain.
متن کاملAcceleration Framework for FPGA Implementation of OpenVX Graph Pipelines
Computer vision processing is computationally expensive and several acceleration solutions have been proposed. Among them, FPGAs offer a promising direction. Vision application are typically written in languages such as C/C++ and they are often difficult to compile into an efficient FPGA implementation. OpenVX is a set of basic, widely used vision kernels. Vision pipelines can be defined as gra...
متن کاملSynthesizing FPGA Circuits from Parallel Programs
From silicon to science : the long road to production reconfigurable supercomputing p. 2 The von Neumann syndrome and the CS education dilemma p. 3 Optimal unroll factor for reconfigurable architectures p. 4 Programming reconfigurable decoupled application control accelerator for mobile systems p. 15 DNA physical mapping on a reconfigurable platform p. 27 Hardware BLAST algorithms with multi-se...
متن کامل